The present invention relates generally to an integrated circuit (IC) design, and more particularly to a layout design for an electrostatic discharge (ESD) protection circuit.
A gate oxide of a metal-oxide-semiconductor (MOS) device of an IC is most susceptible to damage caused by ESD. The gate oxide may be destroyed by being contacted with a voltage only a few volts higher than a supply voltage of the IC. Electrostatic voltages from common environmental sources can easily reach thousands, or even tens of thousands of volts. Such voltages are destructive even though the charge and any resulting current are extremely small. For this reason, an ESD protection circuit is often implemented along with other core circuits in an IC in order to discharge any static electric charge, before it damages the IC.
Silicon-on-insulator (SOI) technology becomes more and more popular for low-voltage, high-speed applications because of its advantages over bulk-silicon technology, such as latch-up immunity and smaller junction capacitance. A diode is a conventional ESD protection device used in the SOI technology. The diode is one of the powerful devices used for on-chip ESD protection due to its low trigger voltage, low turn-on resistance, and high ESD robustness. However, this conventional diode alone does not provide an adequate protection against ESD charges.
Another conventional device often used for ESD protection against the ESD charges is the grounded-gate NMOS (GGNMOS) device constructed by using SOI technology. The GGNMOS device is featured by having a poly-silicon gate layer connected to ground. However, the GGNMOS does not provide adequate ESD protection against negative ESD charges.
Therefore, desirable in the art of the ESD protection circuit in SOI technology are layout structures for ESD protection circuits that provide adequate protection against both the positive and negative ESD charges.